1. Technical Field
The present invention relates in general to designing and simulating digital devices, modules and systems in a distributed simulation environment. In particular, the present invention relates to a method and system that improve a distributed simulation environment by permitting a user to selectively compile instrumentation entities into a simulation model.
2. Description of the Related Art
In a typical digital design process, verifying the logical correctness of a digital design and debugging the design (if necessary) are important steps of the design process performed prior to developing a circuit layout. Although it is certainly possible to test a digital design by actually building the digital design, digital designs, particularly those implemented by integrated circuitry, are typically verified and debugged by simulating the digital design on a computer, due in part to the time and expense required for integrated circuit fabrication.
In a typical automated design process, a circuit designer enters into an electronic computer-aided design (ECAD) system a high-level description of the digital design to be simulated utilizing a hardware description language (HDL), such as VHDL, thus producing a digital representation of the various circuit blocks and their interconnections. In the digital representation, the overall circuit design is frequently divided into smaller parts, hereinafter referred to as design entities, which are individually designed, often by different designers, and then combined in a hierarchical manner to create an overall model. This hierarchical design technique is very useful in managing the enormous complexity of the overall design and facilitates error detection during simulation. After initial development of the digital representation of the design has been accomplished, the ECAD system compiles the digital representation of the design into a simulation model having a format best suited for simulation.
A simulator then exercises the simulation model to detect logical errors in the digital design. A simulator is typically a software tool that operates on the simulation model by applying a list of input stimuli representing inputs of the digital system. The simulator generates a numerical representation of the response of the circuit to the input stimuli, which response may then either be viewed on a display as a list of values or further interpreted, often by a separate software program, and presented on the display in graphical form. The simulator may be run either on a general-purpose computer or on another piece of electronic apparatus specially designed for simulation. Simulators that run entirely in software on a general-purpose computer are referred to as “software simulators,” and simulators that run with the assistance of specially designed electronic apparatus are referred to as “hardware simulators.”
As digital designs have become increasingly complex, digital designs are commonly simulated at several levels of abstraction, for example, at functional, logical and circuit levels. At the functional level, system operation is described in terms of a sequence of transactions between registers, adders, memories and other functional units. Simulation at the functional level is utilized to verify the high-level design of digital systems. At the logical level, a digital system is described in terms of logic elements such as logic gates and flip-flops. Simulation at the logical level is utilized to verify the correctness of the logic design. At the circuit level, each logic gate is described in terms of its circuit components such as transistors, impedances, capacitances, and other such devices. Simulation at the circuit level provides detailed information about voltage levels and switching speeds.
In order to verify the results of any given simulation run, custom-developed programs written in high-level languages such as C or C++, referred to as a reference model, are written to process input stimuli (also referred to as test vectors) to produce expected results of the simulation run. The test vector is then run against the simulation execution model by the simulator. The results of the simulation run are then compared to the results predicted by the reference model to detect discrepancies, which are flagged as errors. Such a simulation check is known in the verification art as an “end-to-end” check.
It is often the case that events of interest are quite complex in that they occur over many cycles and are composed of temporally complex interactions of a large number of signals within the given simulation model. In order to facilitate the generation and reporting of events of interest within the simulation model, the above-referenced patent application disclosed the definition of “instrumentation entities” for generating and reporting occurrences of instrumentation events within the simulation model. By associating such instrumentation entities with selected design entities comprising the digital design under simulation, complex instrumentation events can be efficiently defined, generated and reported, thus enhancing the verification process.
Although the overall simulation process is improved by the ability to efficiently instrument simulation models to detect occurrences of events of interest, the present invention recognizes that the compilation of a large number of instrumentation entities into a simulation models entails concomitant overhead in the execution of the simulation model and an increase in the amount of simulation data that must be managed. At small levels of scale (e.g., a simulation model of a portion of an integrated circuit chip) and with a relatively small number of instrumentation entity instances, the processing overhead and growth in simulation data occasioned by the instrumentation entities compiled into the simulation model are generally acceptable. However, as the scale of the simulation model increases (e.g., simulation models of large integrated circuits or large systems containing numerous integrated circuits) and the number of instrumentation entity instances grows, the simulation data and processing overhead attributable to instruction entities can become undesirably large, significantly degrading simulation performance.
Consequently, the present invention recognizes that it would be useful and desirable to enable a simulation user to control the amount of processing overhead and simulation data attributable to the inclusion of instrumentation entities in the compilation of a given simulation model.